DE Notes

Full Adder — Circuit, Truth Table, K-Map and Carry Propagation

Complete guide to full adder: truth table, K-map minimization for Sum and Carry-out, logic circuit, 4-bit ripple carry adder, carry lookahead adder introduction, and Verilog code.

What is a Full Adder?

A full adder adds three 1-bit inputs — A, B, and Carry-in (Cin) — and produces a Sum and Carry-out (Cout). The Cin allows full adders to be cascaded for multi-bit addition.

Example

┌──────────────┐ A ─────┤ ├──── Sum (S) B ─────┤ Full Adder │ Cin ─────┤ ├──── Carry-out (Cout) └──────────────┘

Boolean Expressions (from K-map)

Sum K-map (3-variable):

Example

Sum = A ⊕ B ⊕ Cin

Sum is the XOR of all three inputs — produces 1 when an odd number of inputs are 1.

Cout K-map:

- AB	Cout when A=1, B=1 (regardless of Cin)
- A·Cin	when A=1, Cin=1
- B·Cin	when B=1, Cin=1

Logic Circuit

Implementation using two half adders:

A ─┐ ┌─── Sum B ─┴──[Half Adder 1]───┬┴──[Half Adder 2]──── Sum S1 ───┘ ↑ C1 ──────────┐│ Cin ────┘│ └──[OR]──── Cout C1 C2 ──────────── Cout

More precisely:

Example

A, B → Half Adder 1 → S1, C1 S1, Cin → Half Adder 2 → Sum, C2 Cout = C1 OR C2

Gate count: 2 XOR + 2 AND + 1 OR = 5 gates

4-bit Ripple Carry Adder

Cascading 4 full adders (with the first Cin tied to 0):

Example

A3B3 A2B2 A1B1 A0B0 ││ ││ ││ ││ ┌──┐ ┌──┐ ┌──┐ ┌──┐ Cout ◄─┤FA│◄─C3─┤FA│◄─C2─┤FA│◄─C1─┤FA│◄─ Cin=0 └──┘ └──┘ └──┘ └──┘ │ │ │ │ S3 S2 S1 S0 Result: S3 S2 S1 S0 (4-bit sum), Cout = carry out

Example: Add 0111 (7) + 0101 (5):

Example

0 1 1 1 + 0 1 0 1 --------- 1 1 0 0 = 12 ✓

Problem: Carry ripple delay Each adder must wait for carry from previous stage. For n-bit adder: total delay = n × (full adder delay). For 16-bit: 16 × 3ns = 48ns.

Solution: Carry Lookahead Adder Computes all carries simultaneously using:

Generate: G = A·B (this stage always generates a carry)
Propagate: P = A⊕B (this stage propagates an incoming carry)

Example

C1 = G0 + P0·C0 C2 = G1 + P1·G0 + P1·P0·C0 C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0

All carries computed in 2 gate delays regardless of bit width!

Verilog

Example

module full_adder ( input wire A, input wire B, input wire Cin, output wire Sum, output wire Cout ); assign Sum = A ^ B ^ Cin; assign Cout = (A & B) | (B & Cin) | (A & Cin); endmodule // 4-bit ripple carry adder module adder_4bit ( input wire [3:0] A, input wire [3:0] B, input wire Cin, output wire [3:0] Sum, output wire Cout ); wire c1, c2, c3; full_adder fa0 (.A(A[0]), .B(B[0]), .Cin(Cin), .Sum(Sum[0]), .Cout(c1)); full_adder fa1 (.A(A[1]), .B(B[1]), .Cin(c1), .Sum(Sum[1]), .Cout(c2)); full_adder fa2 (.A(A[2]), .B(B[2]), .Cin(c2), .Sum(Sum[2]), .Cout(c3)); full_adder fa3 (.A(A[3]), .B(B[3]), .Cin(c3), .Sum(Sum[3]), .Cout(Cout)); endmodule

Interview Questions

Q1: What are the Boolean expressions for Sum and Cout of a full adder? Sum = A ⊕ B ⊕ Cin (three-input XOR). Cout = A·B + B·Cin + A·Cin = majority function (output is 1 when 2 or more of the 3 inputs are 1).

Q2: How is a full adder constructed from two half adders? Half Adder 1: inputs A, B → outputs S1 = A⊕B, C1 = A·B. Half Adder 2: inputs S1, Cin → outputs Sum = S1⊕Cin = A⊕B⊕Cin, C2 = S1·Cin. Final Cout = C1 OR C2.

Q3: What is the propagation delay problem in ripple carry adders? In a ripple carry adder, each full adder must wait for the carry from the previous stage before computing its result. For an n-bit adder, the worst-case delay = n × (carry delay per stage). This grows linearly with bit width, making it slow for wide additions (e.g., 32-bit, 64-bit).

Q4: Why is carry lookahead faster than ripple carry? Carry lookahead computes all intermediate carries simultaneously in parallel using generate (G=AB) and propagate (P=A⊕B) signals. The delay is O(log n) for the lookahead logic, compared to O(n) for ripple carry — significantly faster for wide adders.

Q5: How many full adders are needed for an n-bit ripple carry adder? Exactly n full adders (one per bit position). The first position uses Cin=0 (or a half adder), each subsequent position receives carry from the previous one.

Exam Focus

Revise definitions, diagrams, examples, and short-answer points for Full Adder — Circuit, Truth Table, K-Map and Carry Propagation.

Interview Use

Prepare one clear explanation, one practical example, and one common mistake for this Digital Electronics topic.

Search Terms

digital-electronics, digital electronics, digital, electronics, combinational, circuits, full, adder

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DE Notes

Full Adder — Circuit, Truth Table, K-Map and Carry Propagation

Complete guide to full adder: truth table, K-map minimization for Sum and Carry-out, logic circuit, 4-bit ripple carry adder, carry lookahead adder introduction, and Verilog code.

What is a Full Adder?

A full adder adds three 1-bit inputs — A, B, and Carry-in (Cin) — and produces a Sum and Carry-out (Cout). The Cin allows full adders to be cascaded for multi-bit addition.

Example

Boolean Expressions (from K-map)

Sum K-map (3-variable):

Example

Sum = A ⊕ B ⊕ Cin

Sum is the XOR of all three inputs — produces 1 when an odd number of inputs are 1.

Cout K-map:

- AB	Cout when A=1, B=1 (regardless of Cin)
- A·Cin	when A=1, Cin=1
- B·Cin	when B=1, Cin=1

Logic Circuit

Implementation using two half adders:

More precisely:

Example

A, B → Half Adder 1 → S1, C1 S1, Cin → Half Adder 2 → Sum, C2 Cout = C1 OR C2

Gate count: 2 XOR + 2 AND + 1 OR = 5 gates

4-bit Ripple Carry Adder

Cascading 4 full adders (with the first Cin tied to 0):

Example

Example: Add 0111 (7) + 0101 (5):

Example

0 1 1 1 + 0 1 0 1 --------- 1 1 0 0 = 12 ✓

Problem: Carry ripple delay Each adder must wait for carry from previous stage. For n-bit adder: total delay = n × (full adder delay). For 16-bit: 16 × 3ns = 48ns.

Solution: Carry Lookahead Adder Computes all carries simultaneously using:

Generate: G = A·B (this stage always generates a carry)
Propagate: P = A⊕B (this stage propagates an incoming carry)

Example

C1 = G0 + P0·C0 C2 = G1 + P1·G0 + P1·P0·C0 C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0

All carries computed in 2 gate delays regardless of bit width!

Verilog

Example

Interview Questions

Exam Focus

Revise definitions, diagrams, examples, and short-answer points for Full Adder — Circuit, Truth Table, K-Map and Carry Propagation.

Interview Use

Prepare one clear explanation, one practical example, and one common mistake for this Digital Electronics topic.

Search Terms

digital-electronics, digital electronics, digital, electronics, combinational, circuits, full, adder

Continue learning this concept

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