Timing Diagrams in Sequential Circuits — Clock, Setup, Hold Time Analysis

Key Timing Parameters

Maximum Clock Frequency

The clock period must accommodate the worst-case path:

Maximum frequency:

Example: tcq = 3ns, combinational logic delay = 8ns, tsu = 2ns

Hold Time Constraint

If the minimum combinational delay is too small, data can change at the destination flip-flop while it's still sampling. This is fixed by adding buffer delay.

Drawing a Timing Diagram — Example

Circuit: 2-bit ripple counter (two T flip-flops, T=1, negative edge triggered)

Critical Path Analysis

The critical path is the longest combinational delay path between any two flip-flops. It determines maximum operating frequency.

For a 4-bit ripple carry adder between registers:

A carry lookahead adder reduces this to ~3 gate delays regardless of bit width.

Interview Questions

Q1: What is metastability? Metastability occurs when a flip-flop's setup or hold time is violated. The flip-flop enters an indeterminate analog state where Q is between valid 0 and 1. After an unpredictable time, it resolves to a valid state — but may already have caused errors. Metastability cannot be eliminated, only reduced by good design and proper synchronization.

Q2: How does pipelining increase throughput without changing fmax of individual stages? Pipelining inserts registers between stages. Each stage now only needs to complete in one clock period (not the entire computation). fmax = 1/(longest_single_stage_delay + register_overhead). Total latency increases (more stages), but throughput improves because stages execute concurrently.

Q3: What is a clock skew and why is it a problem? Clock skew is the difference in arrival time of the clock signal at different flip-flops due to routing delays. Positive skew (clock arrives later at destination FF) can relax setup time but tighten hold time. Negative skew can cause hold time violations. Large skew limits operating frequency and must be minimized in high-speed design.