Half Adder — Circuit, Truth Table, Boolean Expression and Verilog

What is a Half Adder?

A half adder is the simplest combinational circuit for binary addition. It adds two 1-bit binary inputs and produces a Sum and a Carry output.

"Half" because: It cannot handle a carry-in from a previous bit position. For multi-bit addition, a full adder is needed.

Boolean Expressions

From the truth table:

Verification:

• S = A⊕B: true only when A≠B (exactly one input is 1) ✓
• C = A·B: true only when both A=1 AND B=1 ✓

Logic Circuit

Gate count: 1 XOR gate + 1 AND gate = 2 gates total

Alternative Implementation Using NAND Gates Only

Half adder can be built using only NAND gates (universal gate):

Uses 4 NAND gates.

Verilog Implementation

Limitation of Half Adder

A half adder can only add two single bits. In a multi-bit addition (e.g., 4-bit numbers), each bit position (except the LSB) may receive a carry from the previous position. The half adder cannot accept a carry-in, so it is only suitable for the least significant bit (LSB) of a multi-bit adder.

Solution: Use a Full Adder for all other bit positions — it has three inputs: A, B, and Carry-in.

Interview Questions

Q1: What are the Boolean expressions for Sum and Carry in a half adder? Sum = A ⊕ B (XOR), Carry = A · B (AND).

Q2: Why is it called a "half" adder? It adds only two inputs (A and B) and cannot process a carry-in from a less significant bit. A full adder handles three inputs (A, B, Cin), making it a "complete" adder for cascading. The half adder is only "half" the solution for multi-bit addition.

Q3: Can a half adder be built using only NAND gates? Yes. Using 4 NAND gates: S = NAND(NAND(A,NAND(A,B)), NAND(B,NAND(A,B))), C = NAND(NAND(A,B), NAND(A,B)) = NOT(NAND(A,B)) with one additional gate. This demonstrates NAND's universality.

Q4: What is the output of a half adder when A=1, B=1? Sum = 1⊕1 = 0, Carry = 1·1 = 1. Result is binary 10 = decimal 2, which is correct (1+1=2).