Asynchronous Counters — Ripple Counter Design and Analysis

What is a Ripple Counter?

In an asynchronous (ripple) counter, only the first flip-flop is clocked by the external clock. Each subsequent flip-flop is clocked by the output (Q or Q̄) of the previous one. The clock "ripples" through the chain.

Propagation Delay Problem

Each flip-flop adds delay tpd before triggering the next:

Intermediate glitch states: During settling, counter passes through invalid intermediate states. For example, going from 0111 to 1000:

These glitch states can cause errors in circuitry connected to counter outputs.

MOD-N Ripple Counter Using CLR

Example: MOD-5 counter (0–4) using 3-bit ripple counter:

Connect CLR when count = 5 (101):

Timing: 000→001→010→011→100→101→(glitch→000)

IC 7493: 4-Bit Ripple Counter

Notes:

• CKA clocks FF0 (QA), CKB clocks FF1 (QB,QC,QD) → connect QA to CKB for 4-bit operation
• R0(1) AND R0(2) both HIGH → asynchronous reset to 0000
• Use R0 inputs for MOD-N operation

MOD-10 (decade counter) using 7493: Connect QD and QB to R0(1), R0(2): reset when count=1010=10.

Comparison with Synchronous Counters

Interview Questions

Q1: In a 4-bit ripple counter with tpd=20 ns, what is the maximum operating frequency? Worst case delay = 4 × 20 = 80 ns. Maximum frequency = 1/80ns = 12.5 MHz. Additionally, the counter output must stabilize before being read, so the period must be at least 80 ns.

Q2: Why does a ripple counter show transient/glitch states? Because each flip-flop has its own propagation delay and they don't all change simultaneously. Going from 7 (0111) to 8 (1000): Q0 changes first (→0), then Q1 (→0), then Q2 (→0), then Q3 (→1). Intermediate states 0110, 0100, 0000 appear briefly before settling at 1000.

Q3: What is the maximum count of an n-bit ripple counter? 2^n - 1. An n-bit counter counts from 0 to 2^n-1 (total 2^n states). For MOD-N operation, add external reset logic.

Q4: How do you build a MOD-6 ripple counter using 7493? Use 3 bits (QA, QB, QC). Connect QA to CKB. Connect QC (MSB=4) and QB (bit 1=2, so QB·QC=6) to R0: R0(1)=QB, R0(2)=QC → reset when QB=1 AND QC=1 → reset at count 110=6. Sequence: 000→001→010→011→100→101→(110→reset)→000.