Latches — SR Latch, D Latch, Gated Latch Complete Guide

Latch vs Flip-Flop

Latch: Q follows input D continuously while Enable=1 Flip-flop: Q only captures D at the instant of the clock edge

D Latch (Transparent Latch)

The D latch eliminates the SR forbidden state by connecting R = S̄ = D̄.

Truth Table:

When EN=1: Q = D (transparent — D passes through directly) When EN=0: Q holds last value

Gated D Latch — Timing

Key hazard: If D changes while EN=1 and there's logic feedback, the output can oscillate — this is why flip-flops are preferred.

8-bit Transparent Latch — 74LS373

The 74LS373 contains 8 D latches with common OE (output enable) and LE (latch enable):

Used in: 8085 microprocessor address/data bus demultiplexing, bus interfacing.

Interview Questions

Q1: Why are latches avoided in synchronous digital design? Latches are level-sensitive — they remain transparent (output follows input) for the entire duration the enable is high. This creates timing windows where glitches on inputs propagate to outputs, making static timing analysis difficult. Flip-flops capture only at a single clock edge, making timing analysis straightforward and predictable.

Q2: When are latches actually used intentionally? In ASIC/VLSI design, latches are used for clock gating (power saving), time-borrowing in pipeline stages (allows paths to borrow time from adjacent stages), and in some FPGA LUT-based implementations. They use slightly less area than flip-flops in custom IC design.

Q3: What is the difference between SR latch and D latch? The SR latch has two independent inputs (S for Set, R for Reset) with a forbidden state S=R=1. The D latch has a single data input D where R = D̄, eliminating the forbidden state entirely. The D latch is the more practical, commonly used form.